1. Field of the Invention
The present invention relates to integrated circuit, and particularly relates to a resistive random access memory and the method of operating the same.
2. Description of Prior Art
Recently, a new-type of non-volatile memory technology, the resistive random access memory (RRAM), has attracted much attention due to its high density, non-volatile storage, fast write and read, compatible with CMOS process, and low power consumption. The resistor in an RRAM cell has bi-stable resistance states with good retention and is switchable between states when a large enough voltage or current pulse (or power pulse) is applied.
The RRAM includes an array of memory cells organized in rows and columns as illustrated in FIG. 1, where a memory cell 100 includes a switching resistor 101 and a select transistor 102 (as referred to as 1T1R cell). The select transistor 102 is assumed an n-type MOSFET (or briefly as n-MOS) for selecting the memory cell 100 to perform the read/write operations. The switching resistor 101 has two terminals, one of which is connected to a bit-line 103, and the other is connected to the drain of the select transistor 102. The gate of the select transistor 102 is connected to a word-line 104, and the source of the select transistor 102 is grounded. The bi-stable resistance states of the switching resistor 101 represent the digital data ‘1’ and ‘0’ as corresponding to the high and low resistance states respectively.
FIG. 2 illustrates a conventional method of operating the RRAM in FIG. 1. The method includes a write operation and a read operation.
During the write operation of the selected memory cell, a high voltage VH (+Vcc) is applied to the bit-line 103. The select transistor 102 (n-MOS) can be turned on by applying a voltage (+Vcc) on the gate of the select transistor 102 through the word-line 104, then a large current flows through the switching resistor 101 and the resistance state of the switching resistor 101 can be changed depending on the magnitude of current and pulse duration. The resistance state of the switching resistor 101 can be changed into a low resistance state (referred to as SET operation), or reversely, into a high-resistance state (referred to as RESET operation). It should be noted that by controlling the transient pulse parameter (e.g. height and duration), the RESET operation (to write “1”) and SET operation (to write “0”) can be intentionally performed (not shown in the waveforms of word-line voltage and resistor current in FIG. 2).
During the read operation on the selected memory cell, a lower voltage VL (˜0.05 v to 1 v) is applied to the bit-line 103. Then the select transistor 102 is turned on by applying a voltage (+Vcc) to the word-line 104. The voltage across the switching resistor 101 is small enough to avoid disturb on the resistance state of the resistor 101 and also large enough for the sense amplifier to detect the current through the resistor 101. The stored data in the memory cell 100 is determined by the current measured in sense amplifier, e.g. a larger current represents data ‘0’ (corresponding a smaller resistance) and a smaller current represents data ‘1’ (corresponding to a larger resistance) Typically, the ratio of larger to smaller current shall be >5.
During the write operation of a selected memory cell, those un-selected cells (on the same bit-line 103) experience gate-induced-drain-leakage (GIDL) current flowing through resistors and transistor's drain into the ground due to the bias at gate (i.e. 0 v for un-selected word-lines) and +Vcc at the selected bit-line. Thus, in the conventional RRAM, the GIDL current continuously flowing through the switching resistor and results in disturb and degraded data retention time, . . . etc.
An illustration of the mechanism of GIDL current in an n-MOS is shown in FIG. 3, with components (a) and (b) included in GIDL current. Component (a) is based on the classical model of GIDL related to the holes generated at the interface between the gate oxide and n-type lightly doped drain (LDD) extension, and subsequently flowing toward the p-well (or substrate). FIG. 3a illustrates how the vertical field (perpendicular to the interface of gate oxide and LDD region) results in band-bending of the LDD region and subsequent band-to-band tunneling (BTBT) of valence band electrons into the depleted n+ drain (i.e. holes generated at the interface). The generated holes will flow toward the p-well due to the electrical field from the reverse biased n+ drain to p-well junction. As shown in FIG. 3b, component (b) is related to the hole generation in the bulk near the interface through the reverse biased n+ drain to p-well junction by valence band electron BTBT if the channel doping is high. This valence band electron BTBT current (component (b)) is based on the same mechanism as the well-known “Zener” diode break-down. In 45 nm CMOS node and beyond, the channel doping is significantly high, thus the component (b) is dominating than component (a). While, at earlier CMOS nodes (e.g. 0.25 um and earlier), the channel doping is not high enough, and the component (a) could be dominating. As shown in FIG. 3a (for n-MOS), the drain to gate bias Vgd needs to be negative enough to result in enough band-bending slightly larger than the band-gap (Eg), in this way the BTBT mechanism for components (a) and (b) is triggered. Similarly, in p-type MOSFET (or briefly as p-MOS), electrons occur at the interface of p+ drain by BTBT of holes under “off” bias and GIDL current of electrons flows toward n-well. As well known, GIDL current can be enhanced by various techniques, e.g. eliminating spacer and LDD implant, reversing the doping polarity of poly gate, . . . etc.
It should be noted that the source and drain in MOSFET are typically the same in structure, thus the GIDL current will occur at the source side also as long as Vgs<0 v (for n-MOS), though the original study of the BTBT current was based on the leakage current observed at the drain side and it is traditionally referred to as the gate-induced-“drain”-leakage (GIDL) current.
Various approaches have been proposed in the prior art for suppressing the GIDL phenomena in MOSFET, e.g. increasing the thickness of the gate oxide, reducing LDD doping, less overlap area between gate oxide and LDD, . . . etc. However, there are very few studies toward how to enhance and utilize the GIDL current of the MOSFET for useful device operation.